1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Element isolation such as LOCOS or STI can be mainly used in a semiconductor device. Japanese Patent Laid-Open No. 2005-347325 discloses an element isolation structure including an insulating member arranged in the upper portion of a semiconductor substrate, and a T-shaped, P-type semiconductor region formed in its lower portion. Such a structure can reduce the influence of, for example, noise generated due, for example, to a lattice defect at the interface between the insulator region and the semiconductor region on the circuit operation.
However, it is difficult for the method described in Japanese Patent Laid-Open No. 2005-347325 to warrant stable manufacture due to accumulation of an error, which occurs in the size of an opening formed to implant an impurity, and a resultant error which occurs in the thickness of an insulating film formed in this opening.